Non-volatile memory (NVM) systems are used in a variety of electronic systems and devices. During erase operations for NVM systems, erase pulses are applied to all NVM bit cells in selected block(s), where the body (e.g., well or substrate) of the bit cells is biased to a high positive voltage (e.g., 8.5 volts), and where the gates of the bit cells are biased to a high negative voltage (e.g., −8.5 volts). After each erase pulse completes, an erase recovery operation is performed to discharge the body and gates of the bit cells to target voltage levels (e.g., 3.3 volts and ground, respectively) in order to allow subsequent NVM operations, such as read and verify operations, to proceed safely.
For erase recovery, the size of the NVM block(s) being erased forms an equivalent capacitor between the gate node and the body of the NVM bit cells, thereby affecting how fast the nodes are discharged to target voltages. Operating temperature for the NVM system also impacts the erase recovery rate by impacting device leakage and the strength of bias pump circuitry within the NVM system. If the erase recovery occurs too fast, coupling between the two high voltage nodes being discharged can potentially cause an overshoot of one high voltage node, thereby causing damage to transistor devices in the NVM circuitry. If the erase recovery occurs too slow, higher than expected voltages can be left on the body or gate nodes of the NVM cells, thereby causing hot switching of the high voltage level shifter circuits in subsequent NVM operations that can damage the devices in the NVM circuitry. However, if a large amount of time is allocated for the total erase recovery process to accommodate the too-slow erase recovery rate, the resulting time delay can adversely impact erase performance of the NVM system.